1 module samp_syc_sig(
 2     input clk_25m,
 3     input nrst,
 4     output samp_syc_sig
 5     );
 6 reg[9:0] time_cnt;    
 7 wire comp;
 8 reg samp_syc_sig_reg;
 9 assign samp_syc_sig = samp_syc_sig_reg;
10 always @ (negedge clk_25m or negedge nrst) 
11 begin
12     if(!nrst)
13         time_cnt[9:0] <= 10'd0;
14     else
15         if(time_cnt[9:0] < 10'd249)
16             time_cnt[9:0] <= time_cnt[9:0] + 10'd1;
17         else
18             time_cnt[9:0] <= 10'd0;
19 end
20     //以下组合逻辑用于产生start信号
21 assign comp =  (time_cnt[9:0] < 10'd20) ? 1'b1 : 1'b0;    
22 always @ (negedge clk_25m or negedge nrst) 
23 begin
24     if(!nrst)
25         samp_syc_sig_reg <= 1'b0;
26     else
27         samp_syc_sig_reg <= comp;
28 end
29 endmodule
同步时钟生成电路